This invention relates to multiprocessing systems and more particularly to an arbitration system for handling requests for access from a plurality of inputs to a plurality of outputs.
It is desirable in large complex computer systems to have multiple memories or basic storage modules (BSM) and have multiple processors communicating with multiple memories with buffering.
In the prior art, there is known arbitrating systems such as in U.S. Pat. No. 4,473,880 of Budde, et al or U.S. Pat. No. 4,499,538 of Finger, et al that provide some form of arbitration system to several processors or microprocessors with a common bus. These arbitration systems with a common bus are relatively slow systems in that only an input to the bus from one unit can be applied via the bus to an output unit in a given time cycle. Cross point switches such as in a switching matrix as described in U.S. Pat. No. 4,417,245 of Melas, et al couple multiple inputs to multiple outputs simultaneously provided a given input does not want to conflict with another given input at the same output and assumes that some form of separate control is provided. There is no arbitrator involved.